As the performance and data throughput requirements for networking and computing applications increase, the performance and data throughput requirements for many of the required individual subsystems also increase. Transferring data between the main memory and the system processor, for example, is often a significant performance bottleneck in any computing system. Even the fastest standard Dynamic Random Access Memory (DRAM) cannot keep up with the ever increasing bus speeds used on many computing systems.
Synchronous Dynamic RAM (SDRAM) is a type of DRAM that demonstrates improved performance and data throughput. While DRAM has an asynchronous interface (i.e., it immediately reacts to changes in its control inputs), SDRAM has a synchronous interface (i.e., it waits for a clock pulse before responding to its control inputs). Likewise, Double Data Rate (DDR) SDRAM is a further evolution of SDRAM that is used in many computing systems. As originally proposed, SDRAM acts on only the rising edge of the clock signal (i.e., each low-to-high transition). DDR SDRAM, on the other hand, acts on both the rising and falling edges, thereby potentially increasing the data rate by a factor of two. Further performance improvements are obtained in DDR-2 (2×) and QDR-2 (4×) by phase shifting the clock signal to obtain additional rising and falling edges.
SDRAM enjoys wide spread application in both low-end consumer computing applications, as well as in high end networking switches and routers. A DDR2 SDRAM interface protocol, for example, is used for communications between an integrated circuit (e.g., a memory controller) and an external memory. See, e.g., JEDEC Standard, DDR2 SDRAM Specification, JESD79-2A (January 2004), incorporated by reference herein. A parallel bus between the memory controller and the external memory typically carries parallel data that is being read from or written to the external memory. In addition, the memory controller provides a system clock CK to the external memory. In this manner, synchronization among the various signals on the parallel bus can be accomplished, for example, by a phase locked loop that generates the system clock CK. According to the DDR2 SDRAM Specification, the external memory will transmit a number of n+1 bit words DQ[0:n] and a data strobe signal, DQS, back to the controller in response to a read request, RD, from the controller.
The DQS signal and the data bits DQ[0:n] are ideally edge aligned. While the DQS signal is inactive, it is held in an undriven, high impedance (HI-Z) state. The controller should not utilize the DQS signal while it is in the HI-Z state, which would cause unpredictable results in the controller. Therefore, the DQS signal must be gated (e.g., AND or NAND gated) into the controller at the appropriate time (i.e., the time at which it is “safe” for the controller to use the DQS signal as an input). Read preamble and read postamble symbols bracket in time the usable portion of the DQS signal, in a known manner.
A number of techniques have been proposed or suggested for the controller to determine when to process the DQS signal during a read operation. Most techniques, especially for high data rates, rely on a priori design understandings to incorporate critical timing into the controller in a “hard-wired” fashion. It has been found, however, that hard-wiring a single timing relationship into the DDR2 controller reduces the noise margin. In addition, this hard-wired approach also results in the rejection of some system configurations as impossible to meet timing. Further, aging effects could result in erroneous operation of the controller. A need therefore exists for methods and apparatus for adaptive determination of one or more timing signals, such as DDR2 DQS timing, in such ASIC devices.